99 lines
3.3 KiB
Diff
99 lines
3.3 KiB
Diff
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From 20940ef2a397446a209350900d3bd618c3fd5b94 Mon Sep 17 00:00:00 2001
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From: Vasily Khoruzhick <anarsoul@gmail.com>
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Date: Mon, 5 Nov 2018 20:24:28 -0800
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Subject: [PATCH 07/13] mmc: sunxi: add support for automatic delay calibration
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A64 and H6 support automatic delay calibration and Linux driver uses it
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instead of hardcoded delays. Add support for it to u-boot driver.
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Fixes eMMC instability on Pinebook
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Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
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Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Cc: Vagrant Cascadian <vagrant@debian.org>
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Reviewed-by: Jagan Teki <jagan@openedev.com>
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---
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arch/arm/include/asm/arch-sunxi/mmc.h | 6 +++++-
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drivers/mmc/sunxi_mmc.c | 21 ++++++++++++++++++++-
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2 files changed, 25 insertions(+), 2 deletions(-)
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diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
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index d98c53faaa..f2deafddd2 100644
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--- a/arch/arm/include/asm/arch-sunxi/mmc.h
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+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
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@@ -46,7 +46,9 @@ struct sunxi_mmc {
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u32 cbda; /* 0x94 */
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u32 res2[26];
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#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
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- u32 res3[64];
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+ u32 res3[17];
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+ u32 samp_dl;
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+ u32 res4[46];
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#endif
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u32 fifo; /* 0x100 / 0x200 FIFO access address */
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};
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@@ -130,5 +132,7 @@ struct sunxi_mmc {
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#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16)
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#define SUNXI_MMC_COMMON_RESET (1 << 18)
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+#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7)
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+
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struct mmc *sunxi_mmc_init(int sdc_no);
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#endif /* _SUNXI_MMC_H */
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diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
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index 39f15eb423..147eb9b4d5 100644
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--- a/drivers/mmc/sunxi_mmc.c
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+++ b/drivers/mmc/sunxi_mmc.c
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@@ -99,11 +99,16 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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{
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unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
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bool new_mode = false;
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+ bool calibrate = false;
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u32 val = 0;
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if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
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new_mode = true;
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+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
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+ calibrate = true;
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+#endif
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+
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/*
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* The MMC clock has an extra /2 post-divider when operating in the new
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* mode.
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@@ -174,7 +179,11 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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val = CCM_MMC_CTRL_MODE_SEL_NEW;
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setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
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#endif
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- } else {
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+ } else if (!calibrate) {
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+ /*
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+ * Use hardcoded delay values if controller doesn't support
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+ * calibration
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+ */
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val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
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CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
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}
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@@ -228,6 +237,16 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
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rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
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writel(rval, &priv->reg->clkcr);
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+#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
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+ /* A64 supports calibration of delays on MMC controller and we
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+ * have to set delay of zero before starting calibration.
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+ * Allwinner BSP driver sets a delay only in the case of
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+ * using HS400 which is not supported by mainline U-Boot or
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+ * Linux at the moment
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+ */
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+ writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
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+#endif
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+
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/* Re-enable Clock */
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rval |= SUNXI_MMC_CLK_ENABLE;
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writel(rval, &priv->reg->clkcr);
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--
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2.11.0
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