90 lines
3.2 KiB
Diff
90 lines
3.2 KiB
Diff
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From 0ad3393ad032f76e88b4dbd04d36ad84dff75dd6 Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Tue, 2 Jun 2015 15:07:01 +0000
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Subject: [PATCH] xen/pt: mark reserved bits in PCI config space fields
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The adjustments are solely to make the subsequent patches work right
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(and hence make the patch set consistent), namely if permissive mode
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(introduced by the last patch) gets used (as both reserved registers
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and reserved fields must be similarly protected from guest access in
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default mode, but the guest should be allowed access to them in
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permissive mode).
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This is a preparatory patch for XSA-131.
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Signed-off-by: Jan Beulich <jbeulich@suse.com>
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---
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hw/xen/xen_pt.h | 2 ++
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hw/xen/xen_pt_config_init.c | 14 +++++++++-----
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2 files changed, 11 insertions(+), 5 deletions(-)
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diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h
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index 8c9b6c2..f9795eb 100644
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--- a/hw/xen/xen_pt.h
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+++ b/hw/xen/xen_pt.h
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@@ -101,6 +101,8 @@ struct XenPTRegInfo {
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uint32_t offset;
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uint32_t size;
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uint32_t init_val;
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+ /* reg reserved field mask (ON:reserved, OFF:defined) */
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+ uint32_t res_mask;
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/* reg read only field mask (ON:RO/ROS, OFF:other) */
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uint32_t ro_mask;
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/* reg emulate field mask (ON:emu, OFF:passthrough) */
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diff --git a/hw/xen/xen_pt_config_init.c b/hw/xen/xen_pt_config_init.c
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index 9f6c00e..efd8bac 100644
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--- a/hw/xen/xen_pt_config_init.c
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+++ b/hw/xen/xen_pt_config_init.c
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@@ -578,7 +578,7 @@ static XenPTRegInfo xen_pt_emu_reg_header0[] = {
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.offset = PCI_COMMAND,
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.size = 2,
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.init_val = 0x0000,
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- .ro_mask = 0xF880,
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+ .res_mask = 0xF880,
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.emu_mask = 0x0743,
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.init = xen_pt_common_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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@@ -603,7 +603,8 @@ static XenPTRegInfo xen_pt_emu_reg_header0[] = {
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.offset = PCI_STATUS,
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.size = 2,
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.init_val = 0x0000,
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- .ro_mask = 0x06FF,
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+ .res_mask = 0x0007,
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+ .ro_mask = 0x06F8,
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.emu_mask = 0x0010,
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.init = xen_pt_status_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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@@ -980,7 +981,8 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] = {
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.offset = PCI_PM_CTRL,
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.size = 2,
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.init_val = 0x0008,
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- .ro_mask = 0xE1FC,
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+ .res_mask = 0x00F0,
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+ .ro_mask = 0xE10C,
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.emu_mask = 0x810B,
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.init = xen_pt_common_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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@@ -1268,7 +1270,8 @@ static XenPTRegInfo xen_pt_emu_reg_msi[] = {
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.offset = PCI_MSI_FLAGS,
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.size = 2,
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.init_val = 0x0000,
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- .ro_mask = 0xFF8E,
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+ .res_mask = 0xFE00,
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+ .ro_mask = 0x018E,
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.emu_mask = 0x017E,
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.init = xen_pt_msgctrl_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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@@ -1446,7 +1449,8 @@ static XenPTRegInfo xen_pt_emu_reg_msix[] = {
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.offset = PCI_MSI_FLAGS,
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.size = 2,
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.init_val = 0x0000,
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- .ro_mask = 0x3FFF,
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+ .res_mask = 0x3800,
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+ .ro_mask = 0x07FF,
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.emu_mask = 0x0000,
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.init = xen_pt_msixctrl_reg_init,
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.u.w.read = xen_pt_word_reg_read,
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--
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2.2.1
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