gnu: Add yosys.
* gnu/packages/fpga.scm (yosys): New variable. Signed-off-by: Efraim Flashner <efraim@flashner.co.il>
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@ -108,3 +108,83 @@ For synthesis, the compiler generates netlists in the desired format.")
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;; Otherwise would be GPL2+.
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;; You have to accept both GPL2 and LGPL2.1+.
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(license (list license:gpl2 license:lgpl2.1+))))
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(define-public yosys
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(package
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(name "yosys")
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(version "0.6")
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(source (origin
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(method url-fetch)
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(uri
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(string-append "https://github.com/cliffordwolf/yosys/archive/"
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name "-" version ".tar.gz"))
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(sha256
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(base32
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"02j0c0m9dfyjccynalf0aggj6gy20k7iphpkg5cn6sdirlkv8gmx"))
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(file-name (string-append name "-" version "-checkout.tar.gz"))
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(modules '((guix build utils)))
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(snippet
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'(substitute* "Makefile"
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(("ABCREV = .*") "ABCREV = default\n")))))
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(build-system gnu-build-system)
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(arguments
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`(#:test-target "test"
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#:make-flags (list "CC=gcc"
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"CXX=g++"
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(string-append "PREFIX=" %output))
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#:phases
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(modify-phases %standard-phases
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(replace 'configure
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(lambda* (#:key inputs (make-flags '()) #:allow-other-keys)
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(zero? (apply system* "make" "config-gcc" make-flags))))
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(add-after 'configure 'prepare-abc
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(lambda* (#:key inputs #:allow-other-keys)
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(let* ((sourceabc (assoc-ref inputs "abc"))
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(sourcebin (string-append sourceabc "/bin"))
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(source (string-append sourcebin "/abc")))
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(mkdir-p "abc")
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(call-with-output-file "abc/Makefile"
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(lambda (port)
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(format port ".PHONY: all\nall:\n\tcp -f abc abc-default\n")))
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(copy-file source "abc/abc")
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(zero? (system* "chmod" "+w" "abc/abc")))))
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(add-before 'check 'fix-iverilog-references
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(lambda* (#:key inputs native-inputs #:allow-other-keys)
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(let* ((xinputs (or native-inputs inputs))
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(xdirname (assoc-ref xinputs "iverilog"))
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(iverilog (string-append xdirname "/bin/iverilog")))
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(substitute* '("./manual/CHAPTER_StateOfTheArt/synth.sh"
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"./manual/CHAPTER_StateOfTheArt/validate_tb.sh"
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"./techlibs/ice40/tests/test_bram.sh"
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"./techlibs/ice40/tests/test_ffs.sh"
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"./techlibs/xilinx/tests/bram1.sh"
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"./techlibs/xilinx/tests/bram2.sh"
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"./tests/bram/run-single.sh"
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"./tests/realmath/run-test.sh"
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"./tests/simple/run-test.sh"
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"./tests/techmap/mem_simple_4x1_runtest.sh"
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"./tests/tools/autotest.sh"
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"./tests/vloghtb/common.sh")
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(("if ! which iverilog") "if ! true")
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(("iverilog ") (string-append iverilog " "))
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(("iverilog_bin=\".*\"") (string-append "iverilog_bin=\""
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iverilog "\"")))
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#t))))))
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;; TODO add xdot [patch the path to it here] as soon as I find out where it is.
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(native-inputs
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`(("pkg-config" ,pkg-config)
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("python" ,python)
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("bison" ,bison)
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("flex" ,flex)
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("gawk" , gawk) ; for the tests and "make" progress pretty-printing
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("tcl" ,tcl) ; tclsh for the tests
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("iverilog" ,iverilog))) ; for the tests
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(inputs
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`(("tcl" ,tcl)
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("readline" ,readline)
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("libffi" ,libffi)
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("abc" ,abc)))
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(home-page "http://www.clifford.at/yosys/")
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(synopsis "FPGA Verilog RTL synthesizer")
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(description "Yosys synthesizes Verilog-2005.")
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(license license:isc)))
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