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gnu: iverilog: Update to 10.3. 

* gnu/packages/fpga.scm (iverilog): Update to 10.3.
This commit is contained in:
Tobias Geerinckx-Rice 2019-08-26 15:28:44 +02:00
parent 24b03073e5
commit f27cb0f1dd
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1 changed files with 4 additions and 4 deletions
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gnu/packages/fpga.scm
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@ -85,20 +85,20 @@ formal verification.")
(define-public iverilog (define-public iverilog
(package (package
(name "iverilog") (name "iverilog")
(version "10.2") (version "10.3")
(source (origin (source (origin
(method url-fetch) (method url-fetch)
(uri (uri
(string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/" (string-append "ftp://ftp.icarus.com/pub/eda/verilog/v10/"
"verilog-" version ".tar.gz")) "verilog-" version ".tar.gz"))
(sha256 (sha256
(base32 (base32
"0075x5nsxwkrgn7b3635il9kw7mslckaji518pdmwdrdn7fxppln")))) "1vv88ckvfwq7mrysyjnilsrcrzm9d173kp9w5ivwh6rdw7klbgc6"))))
(build-system gnu-build-system) (build-system gnu-build-system)
(native-inputs (native-inputs
`(("flex" ,flex) `(("flex" ,flex)
("bison" ,bison) ("bison" ,bison)
("ghostscript" ,ghostscript))) ; ps2pdf ("ghostscript" ,ghostscript))) ; ps2pdf
(home-page "http://iverilog.icarus.com/") (home-page "http://iverilog.icarus.com/")
(synopsis "FPGA Verilog simulation and synthesis tool") (synopsis "FPGA Verilog simulation and synthesis tool")
(description "Icarus Verilog is a Verilog simulation and synthesis tool. (description "Icarus Verilog is a Verilog simulation and synthesis tool.